Active circuit for synthesizing an inductor

ABSTRACT

The present invention is related to an apparatus comprising an active circuit, said circuit synthesising a self-induction. The invention is characterised in that said active circuit comprises only one Operational Amplifier.

FIELD OF THE INVENTION

[0001] The present invention is related to active circuits, in particular active inductors, which are incorporated in integrated circuits.

STATE OF THE ART

[0002] Active inductors have been described, for example in document U.S. Pat. NO. 6,028,496, which is related to a device comprising two Operational Amplifiers (OPAMPS). The active inductor of this document includes an inverting amplifier of a common source (common emitter) type, which inversely amplifies an input signal and outputs the amplified signal as an output signal, a non-inverting amplifier of a common gate (common base) type, which non-inversely amplifies the output signal and the amplified signal as the input signal, a capacitor connected between the input signal and a reference signal, and a biasing portion for biasing the inverting amplifier and the non-inverting amplifier.

[0003] A general drawback of these existing active inductors is the fact that they all comprise at least two Operational Amplifiers, leading to a relatively high power consumption.

AIMS OF THE INVENTION

[0004] The present invention aims to provide an active inductor which consumes less power compared to the active inductors belonging to the current state of the art.

SUMMARY OF THE INVENTION

[0005] The present invention is related to an apparatus comprising an active circuit, said circuit synthesising an inductor, characterised in that said circuit comprises one Operational Amplifier.

[0006] According to a preferred embodiment, the invention is related to an apparatus comprising an active circuit, wherein said circuit comprises:

[0007] an Operational Amplifier with a non-inverting input terminal, an inverting input terminal, a non-inverting output terminal and an inverting output terminal,

[0008] a first resistor R1 and a first capacitance C1, connected in cascade between said inverting input terminal and a first output terminal of said active circuit,

[0009] a second resistor R1′, having the same resistance as R1, and a second capacitance C1′, having the same capacitance value as C1, connected in cascade between said non-inverting input terminal and a second output terminal of said active circuit,

[0010] a third resistor R2 and a fourth resistor R3, connected in cascade between said non-inverting input terminal and said first output terminal of said circuit,

[0011] a fifth resistor R2′, having the same resistance as R2, and a sixth resistor R3′, having the same resistance as R3, said resistors R2′ and R3′ being connected in cascade between said inverting input terminal and said second output terminal of said circuit,

[0012] a seventh resistor Rx and a third capacitance Cx, connected in parallel, and coupled between said inverting output terminal and a common node of said third resistor R2 and said fourth resistor R3,

[0013] an eighth resistor Rx′, having the same resistance as Rx, and a fourth capacitance Cx′, having the same capacitance value as Cx, said resistor Rx′ and said capacitance Cx′ being connected in parallel, and coupled between said non-inverting output terminal and a common node of said fifth resistor R2′ and said sixth resistor R3′,

[0014] a ninth resistor R4 connected between said inverting output terminal and said first output terminal of said circuit, and an tenth resistor R4′, connected between said non-inverting output terminal and said second output terminal of said circuit.

[0015] According to the preferred embodiment of the present invention, the resistance values of R4 and R4′ obey the following formula: ${R4} = {{R4}^{\prime} = \frac{{\left( {{{C1} \cdot {R1}} + {\left( {{2{C1}} - {Cx}} \right) \cdot {Rx}}} \right) \cdot {R3}} + {{C1} \cdot {R1} \cdot {Rx}}}{{{Cx} \cdot {Rx}} - {{C1} \cdot {R1}}}}$

[0016] According to a further embodiment, the invention is related to an apparatus wherein the inductor synthesised by said active circuit is tuneable. This may be realised by making the capacitors C1, C1′, Cx and Cx′ tuneable.

[0017] According to another embodiment, the ratio between C1 and Cx is constant.

[0018] According to another embodiment, the value Rx.Cx is greater than R1.C1.

SHORT DESCRIPTION OF THE DRAWINGS

[0019]FIG. 1 represents the circuit of an active inductor according to the present invention.

DETAILED DESCRIPTION OF THE INVENTION

[0020] Referring to FIG. 1, the device according to a preferred embodiment of the invention is hereafter disclosed. The main characteristic of the invention is the fact that an active circuit is proposed, for synthesising an inductor, comprising only one Operational Amplifier.

[0021] The circuit can be made tuneable in order to select the self-inductance value. FIG. 1 shows the embodiment wherein the circuit is tuneable, due to the presence of tuneable capacitors. An alternative would be the use of tuneable resistors or a combination of tuneable resistors and capacitors.

[0022] The operational amplifier 1 has non-inverting and inverting input terminals 2 and 3, and non-inverting and inverting output terminals 4 and 5.

[0023] The inverting input terminal 3 of the operational amplifier 1 is coupled via the cascade connection of a resistor R1 and a tuneable capacitance C1 to a first output terminal 6 of the circuit, and is coupled via the cascade connection of two resistors R2′ and R3′ to a second output terminal 7 of the circuit.

[0024] The non-inverting input terminal 2 of the operational amplifier 1 is coupled via the cascade connection of a resistor R1′ and a tuneable capacitance C1′ to the second output terminal 7 of the circuit, and is coupled via the cascade connection of two resistors R2 and R3 to the first output terminal 6 of the circuit.

[0025] The inverting output terminal 5 of the operational amplifier 1 is coupled via a resistor R4 to the first output terminal 6 of the circuit, and via the parallel connection of an tuneable capacitance Cx and a resistor Rx to the common node of the resistors R2 and R3.

[0026] The non-inverting output terminal 4 of the operational amplifier 1 is coupled via a resistor R4′ to the second output terminal 7 of the circuit, and via the parallel connection of a tuneable capacitance Cx′ and a resistor Rx′ to the common node of the resistors R2′ and R3′.

[0027] The following is true for the values of the above described resistors and capacitances:

R1=R1′; R2=R2′; R3=R3′; R4=R4′; Rx=Rx′; C1=C1′; Cx=Cx′

[0028] According to the invention, the resistor R₄ (and R4′) is chosen such that: $R_{4} = {R_{4}^{\prime} = \frac{{\left( {{C_{1} \cdot R_{1}} + {\left( {{2C_{1}} - C_{X}} \right) \cdot R_{X}}} \right) \cdot R_{3}} + {C_{1} \cdot R_{1} \cdot R_{X}}}{{C_{X} \cdot R_{X}} - {C_{1} \cdot R_{1}}}}$

[0029] As a result, the synthesised impedance behaves like the serial connection of a resistor and an inductor:

Z _(SYNTH) =R _(SYNTH) +jωL _(SYNTH).

[0030] Herein: $R_{SYNTH} = {\frac{2 \cdot R_{3} \cdot R_{4}}{R_{3} + R_{4} + R_{X}}\quad {and}}$ $L_{SYNTH} = {\frac{2 \cdot R_{3} \cdot R_{4} \cdot R_{X} \cdot C_{X}}{R_{3} + R_{4} + R_{X}} = {R_{SYNTH} \cdot R_{X} \cdot {C_{X}.}}}$

[0031] This is proven by the following mathematical derivation. The synthesized impedance is given by: $\begin{matrix} {Z_{SYNTH} = {\frac{V_{A} - \left( {- V_{A}} \right)}{I} = \frac{2V_{A}}{I}}} & (1) \end{matrix}$

[0032] with V_(A) being the supply voltage.

[0033] The current 1 shown in FIG. 1, can be written as a function of currents I₁, I₃, and I₄:

I=I ₁ +I ₃ +I ₄  (2)

[0034] I₁, I₃, and I₄ are determined below.

[0035] I₁ can be determined by expressing that the operational amplifier 1 is virtually grounded: $\begin{matrix} {{I_{1} = {\frac{V_{A} - 0}{Z_{1}} = {\frac{V_{A}}{Z_{1}}\quad {Herein}}}},} & (3) \\ {{Z_{1} = {R_{1} + {\frac{1}{{j\omega}\quad C_{1}}\quad {Furthermore}}}},} & (4) \\ {I_{3} = {\frac{V_{A} - V_{B}}{R_{3}}\quad {with}}} & (5) \\ {V_{B} = {R_{2} \cdot I_{2}}} & (6) \end{matrix}$

[0036] Kirchof's law applied at the non-inverting input 2 results in: $\begin{matrix} {{{- I_{1}} + I_{2}} = {\left. 0\Rightarrow I_{2} \right. = {I_{1} = \frac{V_{A}}{Z_{1}}}}} & (7) \end{matrix}$

[0037] Substituting (7) in (6) results in: $\begin{matrix} {V_{B} = {V_{A} \cdot \frac{R_{2}}{Z_{1}}}} & (8) \end{matrix}$

[0038] so that (5) turns into: $\begin{matrix} {I_{3} = {{V_{A} \cdot \frac{1 - \frac{R_{2}}{Z_{1}}}{R_{3}}} = {V_{A} \cdot \frac{Z_{1} - R_{2}}{R_{3} \cdot Z_{1}}}}} & (9) \end{matrix}$

[0039] From FIG. 1, one derives that: $\begin{matrix} {I_{4} = {\frac{V_{A} - V_{C}}{R_{4}}\quad {with}}} & (10) \\ {V_{C} = {V_{B} + {{I_{X} \cdot Z_{X}}\quad {Herein}}}} & (11) \\ {Z_{X} = {{R_{X}//C_{X}} = {\frac{1}{\frac{1}{R_{X}} + {{j\omega}\quad C_{X}}} = \frac{R_{X}}{1 + {{j\omega}\quad {R_{X} \cdot C_{X}}}}}}} & (12) \end{matrix}$

[0040] Kirchof's law applied in the V_(B) node, results in:

I ₃ +I _(x) −I ₂=0→I _(x) =I ₂ −I ₃  (b 13)

[0041] After substitution of (7) and (9) in (13), one obtains: $\begin{matrix} {I_{X} = {{\frac{V_{A}}{Z_{1}} - {V_{A} \cdot \frac{Z_{1} - R_{2}}{R_{3} \cdot Z_{1}}}} = {V_{A} \cdot \frac{R_{2} + R_{3} - Z_{1}}{R_{3} \cdot Z_{1}}}}} & (14) \end{matrix}$

[0042] From equation ( 11), V_(C) can now be derived: $\begin{matrix} {\begin{matrix} {V_{C} = {{V_{A} \cdot \frac{R_{2}}{Z_{1}}} + {V_{A} \cdot \frac{Z_{X} \cdot \left( {R_{2} + R_{3} - Z_{1}} \right)}{R_{3} \cdot Z_{1}}}}} \\ {= {V_{A} \cdot \frac{{R_{3} \cdot R_{2}} + {Z_{X} \cdot \left( {R_{2} + R_{3} - Z_{1}} \right)}}{R_{3} \cdot R_{4} \cdot Z_{1}}}} \end{matrix}\quad} & (15) \end{matrix}$

[0043] (15) can be substituted in equation ( 10), resulting in: $\begin{matrix} {I_{4} = {V_{A} \cdot \frac{{R_{3} \cdot Z_{1}} - {R_{3} \cdot R_{2}} + {Z_{X} \cdot \left( {Z_{1} - R_{2} - R_{3}} \right)}}{R_{3} \cdot R_{4} \cdot Z_{1}}}} & (16) \end{matrix}$

[0044] The expressions found in (3), (9) and (16) are to be substituted in (2) to find the current I: $\begin{matrix} {\begin{matrix} {I = \quad {I_{1} + I_{3} + I_{4}}} \\ {= \quad {V_{A} \cdot \frac{{R_{3} \cdot R_{4}} - {R_{2} \cdot R_{4}} + {Z_{1} \cdot R_{4}} + {R_{3} \cdot Z_{1}} - {R_{3} \cdot R_{2}} + {Z_{X} \cdot \left( {Z_{1} - R_{2} - R_{3}} \right)}}{R_{3} \cdot R_{4} \cdot Z_{1}}}} \\ {= \quad {V_{A} \cdot \frac{{\left( {R_{3} + R_{4}} \right) \cdot \left( {Z_{1} - R_{2}} \right)} + {\frac{R_{3} \cdot R_{4}}{R_{3} + R_{4}} \cdot \left( {R_{3} + R_{4}} \right)} + {Z_{X} \cdot \left( {Z_{1} - R_{2} - R_{3}} \right)}}{R_{3} \cdot R_{4} \cdot Z_{1}}}} \end{matrix}{\quad {{Herein},}}} & (17) \\ {\frac{R_{3} \cdot R_{4}}{R_{3} + R_{4}} = {R_{3}//R_{4}}} & (18) \end{matrix}$

[0045] and consequently: $\begin{matrix} {I = {V_{A} \cdot \frac{{\left( {R_{3} + R_{4}} \right) \cdot \left( {{Z_{1} - R_{2} + R_{3}}//R_{4}} \right)} + {Z_{X} \cdot \left( {Z_{1} - R_{2} - R_{3}} \right)}}{R_{3} \cdot R_{4} \cdot Z_{1}}}} & (19) \end{matrix}$

[0046] R₂ is chosen as specified by (20)

R ₂ =R ₁ +R ₃ //R ₄ ≈R ₁ +R ₃  (20)

[0047] In order to fulfill the approximate equality, R₃ should preferably not be higher than 20% of R₄.

[0048] and by substituting (4) and (12) in (19), the expression for I becomes: $\begin{matrix} {I = {\frac{\left( {R_{3} + R_{4} + R_{X}} \right) \cdot \left( {1 + {{j\omega}{C_{X} \cdot R_{X} \cdot \left( {R_{3} + R_{4}} \right)}} - \frac{2 \cdot C_{1} \cdot R_{3} \cdot R_{X}}{R_{3} + R_{4} + R_{X}}} \right)}{{R_{3} \cdot R_{4} \cdot \left( {1 + {{j\omega C}_{1} \cdot R_{1}}} \right)}1\left( {1 + {{j\omega}\quad {R_{X} \cdot C_{X}}}} \right)} \cdot V_{A}}} & (21) \end{matrix}$

[0049] If R₄ is now chosen such that: $\begin{matrix} {R_{4} = \frac{{\left( {{C_{1} \cdot R_{1}} + {\left( {{2C_{1}} - C_{X}} \right) \cdot R_{X}}} \right) \cdot R_{3}} + {C_{1} \cdot R_{1} \cdot R_{X}}}{{C_{X} \cdot R_{X}} - {C_{1} \cdot R_{1}}}} & (22) \end{matrix}$

[0050] and (21) is substituted into (1), then the synthesized impedance behaves like the serial connection of a resistor and an inductor:

Z _(SYNTH) =R _(SYNTH) +jωL _(SYNTH)  (23)

[0051] with $\begin{matrix} {{R_{S\quad Y\quad N\quad T\quad H} = \frac{2 \cdot R_{3} \cdot R_{4}}{R_{3} + R_{4} + R_{X}}}{and}} & (24) \\ {L_{S\quad Y\quad N\quad T\quad H} = {\frac{2 \cdot R_{3} \cdot R_{4} \cdot R_{X} \cdot C_{X}}{R_{3} + R_{4} + R_{X}} = {R_{S\quad Y\quad N\quad T\quad H} \cdot R_{X} \cdot C_{X}}}} & (25) \end{matrix}$

[0052] The resistor R_(SYNTH) can be made smaller than 1 Ω by choosing a high Rx, while the inductor can be a few μH. In order to keep R4 constant with C1 and Cx variable, a constant ratio should be chosen between C1 and Cx. Typically, Rx.Cx must be greater than R1.C1 in order to have a significantly high inductance with a small resistor value.

[0053] For example:

[0054] R1=R1′=500 ω

[0055] R3=R3′=10 ω

[0056] R2=R2′32 510 ω

[0057] Rx=Rx′=1500 ω

[0058] R4=R4′=82 ω

[0059] RSYNTH=1.1 ω

[0060] Cx/C1=6

[0061] For LSYNTH=2 μH, we find Cx=1.21 nF 

1. An apparatus comprising an active circuit (10), said circuit synthesising an inductor, characterised in that said circuit comprises one Operational Amplifier (1).
 2. An apparatus according to claim 1, wherein said circuit comprises an Operational Amplifier (1) with a non-inverting input terminal (2), an inverting input terminal (3), a non-inverting output terminal (4) and an inverting output terminal (5), a first resistor R1 and a first capacitance C1, connected in cascade between said inverting input terminal (3) and a first output terminal (6) of said active circuit (10), a second resistor R1′, having the same resistance as R1, and a second capacitance C1′, having the same capacitance value as C1, connected in cascade between said non-inverting input terminal (2) and a second output terminal (7) of said active circuit (10), a third resistor R2 and a fourth resistor R3, connected in cascade between said non-inverting input terminal (2) and said first output terminal (6) of said circuit, a fifth resistor R2′, having the same resistance as R2, and a sixth resistor R3′, having the same resistance as R3, said resistors R2′ and R3′ being connected in cascade between said inverting input terminal (3) and said second output terminal (7) of said circuit, a seventh resistor Rx and a third capacitance Cx, connected in parallel, and coupled between said inverting output terminal (5) and a common node of said third resistor R2 and said fourth resistor R3, an eighth resistor Rx′, having the same resistance as Rx, and a fourth capacitance Cx′, having the same capacitance value as Cx, said resistor Rx′ and said capacitance Cx′ being connected in parallel, and coupled between said non-inverting output terminal (4) and a common node of said fifth resistor R2′ and said sixth resistor R3′, a ninth resistor R4 connected between said inverting output terminal (5) and said first output terminal (6) of said circuit, and an tenth resistor R4′, connected between said non-inverting output terminal (4) and said second output terminal (7) of said circuit.
 3. An apparatus according to claim 2, wherein ${R4} = {{R4}^{\prime} = {\frac{{\left( {{{C1} \cdot {R1}} + {{\left( {{2{C1}} - {C\quad x}} \right) \cdot R}\quad x}} \right) \cdot {R3}} + {{{C1} \cdot {R1} \cdot R}\quad x}}{{C\quad {x \cdot R}\quad x} - {{C1} \cdot {R1}}}.}}$


4. An apparatus according to any one of claims 1 to 3, wherein the inductor synthesised by said active circuit is tuneable.
 5. An apparatus according to claim 4, wherein said capacitors C1, C1′, Cx and Cx′ are tuneable.
 6. An apparatus according to any one of the preceding claims, wherein the ratio between C1 and Cx is constant.
 7. An apparatus according to any one of the preceding claims, wherein the value Rx.Cx is greater than R1.C1. 